1. Industrial Field of the Invention
The present invention relates to a method for forming a high speed insulated gate field effect semiconductor device (transistor) suitable for large-scale integration. The semiconductor device according to the present invention is favorably used in microprocessors, microcontrollers, microcomputers, semiconductor memories (IC memories) , etc.
2. Prior Art
Extensive R & D efforts with aim to achieve finer semiconductor devices and higher integration are now in progress. In particular, an outstanding progress has been made in the technology for realizing finer insulated gate field effect semiconductor devices; specifically, in the fabrication of MOSFETs (Metal Oxide Semiconductor type Field-Effect Transistors). The "metal" as used herein refers not only pure metals but also semiconductor materials and alloys thereof with metals, provided that those materials have sufficiently high electric conductivity. Furthermore, the oxide incorporated between the metal and the semiconductor need not always be a pure oxide, and also useful are insulator materials having sufficiently high resistance such as nitrides. Thus, the term "MOS" in a strict sense may not be applied to the cases above, but the term herein is used in a broader meaning in which oxides include nitrides and other insulating materials. In this context, MOSFETs refer to field-effect devices based on the structure described hereinbefore.
Fine MOSFETs are realized by decreasing the width of gates. Decreasing a gate width is equivalent to shortening a channel length. In this manner higher speed is achieved simultaneously with the realization of higher integration, because the carriers can be transferred more rapidly along the channel.
A decrease in the gate width, however, brings about disadvantages known as short channel effects. Particularly important among them is the problem of hot electrons. Let us consider a conventional structure comprising impurity-rich regions, i.e., a source and a drain, and a channel region being doped with an impurity of the other polarity having incorporated therebetween. In such a structure, the electric field at the vicinity of the boundary between the channel region and the impurity-rich regions, which is generated by the potential applied to the source and the drain, increases with decreasing channel length. Thus, a considerably unstable MOSFET is realized as a result.
As a solution to this problem, a novel MOSFET structure known as Lightly Doped Drain (LDD) structure is proposed. A typical type of this structure is described below referring to FIG. 2(D). In FIG. 2(D), the LDD region is shown by a region 27 established at a shallower position with respect to an impurity-rich region 26. The electric field at the vicinity of the boundary between the channel and the impurity-rich regions can be decreased by thus providing the LDD region, and thereby devices which operate stabler have been realized.
In general, the LDD regions are established in such a manner shown schematically in FIG. 2. Though the figure is given specifically for an NMOS, PMOS can be fabricated in a similar manner as well. First, an oxide film and then an electrically conductive film are deposited on a p-type semiconductor substrate, and are then etched to give a gate insulator 22 and a gate 21 as shown in FIG. 2(A). Then, an impurity region 23 (an n.sup.- region) relatively low in impurity concentration is established by, for example, ion bombarding, in a self-aligned manner using the gate as the mask.
An insulator film 24 such as a PSG film is then deposited subsequently on the structure above. This insulator film 24 is removed thereafter by an anisotropic etching process (known also as orientation dependent etching) such as a biased plasma etching. As a result, a structure as shown in FIG. 2(C) can be obtained, with the PSG remaining un-etched on the side of the gate. The PSG residue thus obtained is called a spacer. Then an impurity-rich region (an n.sup.+ region) 26 is established in a self-aligned manner using the spacer 25 as the mask. The n.sup.+ impurity region is then used as a source and a drain for the FET.
An LDD structure having established in this manner reportedly shortens a conventionally feasible channel length of 0.5 .mu.m to 0.1 .mu.m.
However, the LDD structure still cannot provide all the solutions to the problems associated with a short-channeled structure. One of such problems which await solution include the resistance of the gate. Certainly the operating speed would be increased by reducing its width, however, this advantage would be easily canceled out by a decrease in transfer speed if the gate has such a high resistivity. To overcome this problem, countermeasures such as using metal silicides low in resistivity in the place of a conventionally used impurity-rich polycrystalline silicon, or running a low-resistance wiring, e.g., an aluminum wiring, in parallel with the gate are proposed and actually employed. Those measures yet require further alternative means as the width of the gate approaches 0.3 .mu.m or less.
As another solution to the problem above, the ratio of the height to the width of the gate, i.e., the aspect ratio, is increased. An increase in the aspect ratio extends the cross sectional area of the gate and thereby reduces the resistivity thereof. However, this measure also has some limitation in the fabrication of the LDD structure, and hence an aspect ratio of a limited value is only available. More precisely, this limitation is due to the fact that the width of the spacer having etched out depends on the height of the gate. In general, a spacer conventionally available has a width of about 20% or more of the height of the gate. Accordingly, if the LDD region 27 in FIG. 2 were to be established at a width L of 0.1 .mu.m, the gate must be provided at a height h of 0.5 .mu.m or less. If the height h of the gate exceeds 0.5 .mu.m, an L of 0.1 .mu.m or larger results. This leads to an unfavorable increase in resistance between the source and the drain.
Suppose a gate having an h of 0.5 .mu.m and a width W of 1.0 .mu.m, and an LDD having a width L of 0.1 .mu.m are established. If this element were to be further scaled down to a width W of 0.5 .mu.m, an h of 1.0 .mu.m must be realized to maintain the same resistivity. With a W of 0.5 .mu.m and an h of 1.0 .mu.m, however, L becomes 0.2 .mu.m. This signifies that the resistance between the source and the drain at an ON state (a state at which a voltage is applied to a gate electrode and the resistance in the channel region is sufficiently lowered with respect to that of the n.sup.- region) is doubled in spite of the gate being maintained at a constant resistivity. In such a case, the element is expected to respond at a twice faster speed in correspondence to the channel length which have been halved. However, this advantage is canceled out by the doubled resistance between the source and the drain. Accordingly, an element with a higher integration but with no improvement in the response speed is achieved. On the other hand, if an element having an L being maintained to a conventional value were to be achieved, the gate should be established at an h of 0.5 .mu.m. This again results in a resistance twice as large as before, and hence a quick response cannot be obtained.
In practice, the spacer is provided at a width corresponding to 50 to 100% of the height of the gate. Thus, in a conventional process for fabricating an LDD, the gate is fabricated at an aspect ratio of 1 or lower, and mostly 0.2 or lower. Furthermore, the width for a spacer greatly fluctuates and hence it is the reason why transistors give characteristic values differing from one to another. Thus, it can be seen that a conventional process for fabricating an LDD structure does realize a higher stability in a shorter channel and devices with higher integration and quicker response as a consequence, but is in conflict that the fabrication process itself poses hindrance for a still higher integration and quicker response.